This invention relates generally to the chemical-mechanical planarization (CMP) of substrates containing chalcogenide materials (e.g., germanium/antimony/tellurium alloy) on semiconductor wafers and slurry compositions therefor. In particular, the present invention relates to a CMP method using an associated slurry composition that is effective for use in chalcogenide CMP and which affords low defect counts (e.g., scratches incurred during polishing) and low dishing levels on polished substrates following CMP processing. This invention is especially useful for CMP of chalcogenide alloy materials where low defect counts and dishing levels on planarized substrates is desired.
Chalcogenide materials possess the property of undergoing phase changes with different phases having different electrical properties and thereby have potential applications in new memory devices. The Germanium, Antimony, and Tellerium (GST) alloy is one of many in a family of phase change chalcogenide materials being considered for use in future advanced memory devices. If successful, these devices could replace many of the memory chips currently used today (DRAM, Flash, etc.) and become a major new market. The GST material typically is deposited onto the surface of a wafer and into various features etched into the surface of the wafer during the construction of the memory devices. The overburden of material above and between the etched features is required to be removed. The state of the art technique for removing this material overburden is chemical mechanical polishing (CMP).
Memory having access devices using phase change material such as chalcogenide is known; see, for example, U.S. Pat. No. 6,795,338. Such phase change memory devices use phase change materials, i.e., materials that may be electrically switched between a generally amorphous state and a generally crystalline state, for electronic memory applications (as is reported in this patent).
Chemical mechanical planarization (chemical mechanical polishing, CMP) for planarization of semiconductor substrates is now widely known to those skilled in the art and has been described in numerous patents and open literature publications. An introductory reference on CMP is as follows: “Chemical-Mechanical Polish” by G. B. Shinn et al., Chapter 15, pages 415-460, in Handbook of Semiconductor Manufacturing Technology, editors: Y. Nishi and R. Doering, Marcel Dekker, New York City (2000).
In a typical CMP process, a substrate (e.g., a wafer) is placed in contact with a rotating polishing pad attached to a platen. A CMP slurry, typically an abrasive and a chemically reactive mixture, is supplied to the pad during CMP processing of the substrate. During the CMP process, the pad (fixed to the platen) and substrate are rotated while a wafer carrier system or polishing head applies pressure (downward force) against the substrate. The slurry accomplishes the planarization (polishing) process by chemically and mechanically interacting with the substrate film being planarized due to the effect of the rotational movement of the pad relative to the substrate. Polishing is continued in this manner until the desired film on the substrate is removed with the usual objective being to effectively planarize the substrate. Typically CMP slurries for polishing metals, including chalcogenide alloys, contain an abrasive material, such as silica or alumina, suspended in an oxidizing, aqueous medium.
Silicon based semiconductor devices, such as integrated circuits (ICs), typically include a dielectric layer, which can be a low-k dielectric material, silicon dioxide, or other material. Multilevel circuit traces, typically formed from aluminum or an aluminum alloy or copper, are patterned onto the low-k or silicon dioxide substrate. In case of advanced memory devices as referenced supra, chalcogenide materials that are capable of undergoing phase changes may also be deposited in manufacture of these advanced semiconductor devices.
CMP processing is often employed to remove and planarize excess metal (e.g., removal of overburden chalcogenide alloys) at different stages of semiconductor manufacturing. For example, one way to fabricate a multilevel metal (e.g., copper as referenced below) interconnect or planar metal (e.g., copper) circuit traces on a silicon dioxide substrate is referred to as the damascene process. In a semiconductor manufacturing process typically used to form a multilevel copper interconnect, metallized copper lines or copper vias are formed by electrochemical metal deposition followed by copper CMP processing. In a typical process, the interlevel dielectric (ILD) surface is patterned by a conventional dry etch process to form vias and trenches for vertical and horizontal interconnects and make connection to the sublayer interconnect structures. The patterned ILD surface is coated with an adhesion-promoting layer such as titanium or tantalum and/or a diffusion barrier layer such as titanium nitride or tantalum nitride over the ILD surface and into the etched trenches and vias. The adhesion-promoting layer and/or the diffusion barrier layer is then overcoated with copper, for example, by a seed copper layer and followed by an electrochemically deposited copper layer. Electro-deposition is continued until the structures are filled with the deposited metal. Finally, CMP processing is used to remove the copper overlayer, adhesion-promoting layer, and/or diffusion barrier layer, until a planarized surface with exposed elevated portions of the dielectric (silicon dioxide and/or low-k) surface is obtained. The vias and trenches remain filled with electrically conductive copper forming the circuit interconnects.
When one-step metal CMP processing is desired, it is usually important that the removal rate of the metal and barrier layer material be significantly higher than the removal rate for dielectric material in order to avoid or minimize dishing of metal features or erosion of the dielectric. Alternatively, a multi-step metal CMP process may be employed involving the initial removal and planarization of the metal overburden, referred to as a step 1 metal CMP process, followed by a barrier layer CMP process. The barrier layer CMP process is frequently referred to as a barrier or step 2 metal CMP process. Previously, it was believed that the removal rate of the metal and the adhesion-promoting layer and/or the diffusion barrier layer must both greatly exceed the removal rate of dielectric so that polishing effectively stops when elevated portions of the dielectric are exposed. The ratio of the removal rate of a metal to the removal rate of dielectric base is called the “selectivity” for removal of the metal in relation to dielectric during CMP processing of substrates comprised of the metal and dielectric material. When CMP slurries with high selectivity for removal of a metal(s) in relation to a dielectric are used, the metal layer(s) is easily over-polished creating a depression or “dishing” effect in the metal vias and trenches. This feature distortion is unacceptable due to lithographic and other constraints in semiconductor manufacturing.
Another feature distortion that is unsuitable for semiconductor manufacturing is called “erosion.” Erosion is the topography difference between a field of dielectric and a dense array of metallic vias or trenches. In CMP, the materials in the dense array may be removed or eroded at a faster rate than the surrounding field of dielectric. This causes a topography difference between the field of dielectric and the dense metal array.
A typically used CMP slurry has two actions, a chemical component and a mechanical component. An important consideration in slurry selection for metal CMP (e.g., chalcogenide alloy CMP) is “passive etch rate.” The passive etch rate is the rate at which metal is dissolved by the chemical component alone and should be significantly lower than the removal rate when both the chemical component and the mechanical component are involved. A large passive etch rate leads to dishing of the metal trenches and vias, and thus, preferably, the passive etch rate is less than 10 nanometers per minute.
These are two general types of layers that can be polished. The first layer is interlayer dielectrics (ILD), such as silicon oxide and silicon nitride. The second layer is metal layers such as tungsten, copper, aluminum, etc., which are used to connect the active devices or chalcogenide alloys, which are used within the active devices.
In the case of CMP of metals (e.g., chalcogenide alloys), the chemical action is generally considered to take one of two forms. In the first mechanism, the chemicals in the solution react with the metal layer to continuously form an oxide layer on the surface of the metal. This generally requires the addition of an oxidizer to the solution such as hydrogen peroxide, ferric nitrate, periodic acid, etc. Then the mechanical abrasive action of the particles continuously and simultaneously removes this oxide layer. A judicious balance of these two processes obtains optimum results in terms of removal rate and polished surface quality.
In the second mechanism, no protective oxide layer is formed. Instead, the constituents in the solution chemically attack and dissolve the metal, while the mechanical action is largely one of mechanically enhancing the dissolution rate by such processes as continuously exposing more surface area to chemical attack, raising the local temperature (which increases the dissolution rate) by the friction between the particles and the metal and enhancing the diffusion of reactants and products to and away from the surface by mixing and by reducing the thickness of the boundary layer.
While prior art CMP systems are capable of removing a metal overlayer(s) from a silicon dioxide substrate, the systems do not satisfy the rigorous demands of the semiconductor industry. These requirements can be summarized as follows. First, there is a need for high removal rates of metal(s) to satisfy throughput demands. Secondly, there must be excellent topography uniformity across the substrate. Finally, the CMP method must minimize dishing and local erosion effects on polished substrates as well as minimizing defectivity levels to satisfy ever increasing lithographic demands.
There is a significant need for metal CMP process(es) and slurry(s) that are applicable to efficient CMP processing of substrates containing chalcogenide alloys and that afford low dishing and local erosion effects as well as low defectivity levels. These requirements are especially important in view of the fact that the semiconductor industry continues to move towards smaller and smaller feature sizes. The present invention provides a solution to this significant need.